The present invention relates to a copper CMP method and associated slurry composition that afford high removal rates of copper during CMP processing while also affording low dishing values.
Chemical mechanical planarization (chemical mechanical polishing, CMP) for planarization of semiconductor substrates is now widely known to those skilled in the art and has been described in numerous patents and open literature publications. An introductory reference on CMP is as follows: “Chemical-Mechanical Polish” by G. B. Shinn et al., Chapter 15, pages 415-460, in Handbook of Semiconductor Manufacturing Technology, editors: Y. Nishi and R. Doering, Marcel Dekker, New York City (2000).
In a typical CMP process, a substrate (e.g., a wafer) is placed in contact with a rotating polishing pad attached to a platen. A CMP slurry, typically an abrasive and chemically reactive mixture, is supplied to the pad during CMP processing of the substrate. During the CMP process, the pad (fixed to the platen) and substrate are rotated while a wafer carrier system or polishing head applies pressure (downward force) against the substrate. The slurry accomplishes the planarization (polishing) process by chemically and mechanically interacting with the substrate film being planarized due to the effect of the rotational movement of the pad relative to the substrate. Polishing is continued in this manner until the desired film on the substrate is removed with the usual objective being to effectively planarize the substrate. Typically metal CMP slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium.
Silicon based semiconductor devices, such as integrated circuits (ICs), typically include a dielectric layer, which can be a low-k dielectric material, silicon dioxide, or other material. Multilevel circuit traces, typically formed from aluminum or an aluminum alloy or copper, are patterned onto the low-k or silicon dioxide substrate.
CMP processing is often employed to remove and planarize excess metal at different stages of semiconductor manufacturing. For example, one way to fabricate a multilevel copper interconnect or planar copper circuit traces on a silicon dioxide substrate is referred to as the damascene process. In a semiconductor manufacturing process typically used to form a multilevel copper interconnect, metallized copper lines or copper vias are formed by electrochemical metal deposition followed by copper CMP processing. In a typical process, the interlevel dielectric (ILD) surface is patterned by a conventional dry etch process to form vias and trenches for vertical and horizontal interconnects and make connection to the sublayer interconnect structures. The patterned ILD surface is coated with an adhesion-promoting layer such as titanium or tantalum and/or a diffusion barrier layer such as titanium nitride or tantalum nitride over the ILD surface and into the etched trenches and vias. The adhesion-promoting layer and/or the diffusion barrier layer is then overcoated with copper, for example, by a seed copper layer and followed by an electrochemically deposited copper layer. Electro-deposition is continued until the structures are filled with the deposited metal. Finally, CMP processing is used to remove the copper overlayer, adhesion-promoting layer, and/or diffusion barrier layer, until a planarized surface with exposed elevated portions of the dielectric (silicon dioxide and/or low-k) surface is obtained. The vias and trenches remain filled with electrically conductive copper forming the circuit interconnects.
When one-step copper CMP processing is desired, it is usually important that the removal rate of the metal and barrier layer material be significantly higher than the removal rate for dielectric material in order to avoid or minimize dishing of metal features or erosion of the dielectric. Alternatively, a multi-step copper CMP process may be employed involving the initial removal and planarization of the copper overburden, referred to as a step 1 copper CMP process, followed by a barrier layer CMP process. The barrier layer CMP process is frequently referred to as a barrier or step 2 copper CMP process. Previously, it was believed that the removal rate of the copper and the adhesion-promoting layer and/or the diffusion barrier layer must both greatly exceed the removal rate of dielectric so that polishing effectively stops when elevated portions of the dielectric are exposed. The ratio of the removal rate of copper to the removal rate of dielectric base is called the “selectivity” for removal of copper in relation to dielectric during CMP processing of substrates comprised of copper, tantalum and dielectric material. The ratio of the removal rate of tantalum to the removal rate of dielectric base is called the “selectivity” for removal of tantalum in relation to dielectric during CMP processing. When CMP slurries with high selectivity for removal of copper and tantalum in relation to dielectric are used, the copper layers are easily over-polished creating a depression or “dishing” effect in the copper vias and trenches. This feature distortion is unacceptable due to lithographic and other constraints in semiconductor manufacturing.
Another feature distortion that is unsuitable for semiconductor manufacturing is called “erosion.” Erosion is the topography difference between a field of dielectric and a dense array of copper vias or trenches. In CMP, the materials in the dense array maybe removed or eroded at a faster rate than the surrounding field of dielectric. This causes a topography difference between the field of dielectric and the dense copper array.
A typically used CMP slurry has two actions, a chemical component and a mechanical component. An important consideration in slurry selection is “passive etch rate.” The passive etch rate is the rate at which copper is dissolved by the chemical component alone and should be significantly lower than the removal rate when both the chemical component and the mechanical component are involved. A large passive etch rate leads to dishing of the copper trenches and copper vias, and thus, preferably, the passive etch rate is less than 10 nanometers per minute.
In relation to copper CMP, the current state of this technology involves use of a two-step process to achieve local and global planarization in the production of IC chips. During step 1 of a copper CMP process, the overburden copper is removed. Then step 2 of the copper CMP process follows to remove the barrier layer and achieve both local and global planarization. Generally, after removal of overburden copper in step 1, polished wafer surfaces have non-uniform local and global planarity due to differences in the step heights at various locations of the wafer surfaces. Low density features tend to have higher copper step heights whereas high density features tend to have low step heights. Due to differences in the step heights after step 1, step 2 copper CMP selective slurries with respect to tantalum to copper removal rates and copper to oxide removal rates are highly desirable. The ratio of the removal rate of tantalum to the removal rate of copper is called the “selectivity” for removal of tantalum in relation to copper during CMP processing of substrates comprised of copper, tantalum and dielectric material.
There are a number of theories as to the mechanism for chemical-mechanical polishing of copper. An article by D. Zeidler, Z. Stavreva, M. Ploetner, K. Drescher, “Characterization of Cu Chemical Mechanical Polishing by Electrochemical Investigations” (Microelectronic Engineering, 33(104), 259-265 (English) 1997), proposes that the chemical component forms a passivation layer on the copper changing the copper to a copper oxide. The copper oxide has different mechanical properties, such as density and hardness, than metallic copper and passivation changes the polishing rate of the abrasive portion. The above article by Gutmann, et al., entitled “Chemical-Mechanical Polishing of Copper with Oxide and Polymer Interlevel Dielectrics” (Thin Solid Films, 1995), discloses that the mechanical component abrades elevated portions of copper and the chemical component then dissolves the abraded material. The chemical component also passivates recessed copper areas minimizing dissolution of those portions.
These are two general types of layers that can be polished. The first layer is interlayer dielectrics (ILD), such as silicon oxide and silicon nitride. The second layer is metal layers such as tungsten, copper, aluminum, etc., which are used to connect the active devices.
In the case of CMP of metals, the chemical action is generally considered to take one of two forms. In the first mechanism, the chemicals in the solution react with the metal layer to continuously form an oxide layer on the surface of the metal. This generally requires the addition of an oxidizer to the solution such as hydrogen peroxide, ferric nitrate, etc. Then the mechanical abrasive action of the particles continuously and simultaneously removes this oxide layer. A judicious balance of these two processes obtains optimum results in terms of removal rate and polished surface quality.
In the second mechanism, no protective oxide layer is formed. Instead, the constituents in the solution chemically attack and dissolve the metal, while the mechanical action is largely one of mechanically enhancing the dissolution rate by such processes as continuously exposing more surface area to chemical attack, raising the local temperature (which increases the dissolution rate) by the friction between the particles and the metal and enhancing the diffusion of reactants and products to and away from the surface by mixing and by reducing the thickness of the boundary layer.
While prior art CMP systems are capable of removing a copper overlayer from a silicon dioxide substrate, the systems do not satisfy the rigorous demands of the semiconductor industry. These requirements can be summarized as follows. First, there is a need for high removal rates of copper to satisfy throughput demands. Secondly, there must be excellent topography uniformity across the substrate. Finally, the CMP method must minimize dishing and local erosion effects on polished substrates as well as minimizing defectivity levels to satisfy ever increasing lithographic demands.
There is a significant need for copper CMP process(es) and slurry(s) that afford low dishing and local erosion effects especially in view of the fact that the semiconductor industry continues to move towards smaller and smaller feature sizes. The present invention provides a solution to this significant need.